■Intel Corporation

Technology Changes and Challenges

■Presentation Description
Ton Steenman will discuss how Intel's new technology and product lineup, including AtomT processor family and Intel System-on-a-Chip (SoC), will bring the advantages of Intel Architecture to low power and small form factor embedded applications. Embedded products are increasingly required to communicate with each other and with the Internet and perform media processing and rich visualization to stay competitive. The keynote will highlight new Intel technology, architecture and product lines, and will present examples of the advantages of Intel Architectures for several embedded market segments.

■Presenter
Ton Steenman
Vice President, Digital Enterprise Group
General Manager, Infrastructure Processor Division

Ton Steenman is vice president, Digital Enterprise Group, and general manager of the Infrastructure Processor Division. In this capacity, he is responsible for the architecture, development and marketing of microprocessor, network processor and chipset solutions for embedded market segments.

■ARM Ltd.

ARM's MPCore Architecture Performance Enhancements

■Presentation Description
The presentation will introduce details describing the ARM MPCore microarchitecture and its deployment.

■Presenter
John Goodacre
Senior Program Manager

John joined ARM in February 2002 and took responsibility for their platform architecture roadmap and is now responsible for the market development and definition of the ARM MPCore multicore processor technology realized in both the ARM11 MPCore™ - the first integrated SMP core, and more recently the Cortex-A9 MPCore.
Prior to working at ARM, he specialized in enterprise software having worked for Microsoft for 5 years, firstly as Group Program Manager in the Exchange Server group and latterly as a manager for software utilized in mobile phones.
Graduating from the University of York with a BSc in Computer Science, John has over 20 years experience of realizing new technologies in the engineering industry.

■TOSHIBA Corporation Semiconductor Company

New Stream Processor "SpursEngine"

■Presentation Description
The presentation will descrive "SpursEngine", new stream processor integrating SPE (Synergistic Processor Element) cores derived from the Cell Broadband Engine (Cell/B.E.). The concept and architecture of SpursEngine will be covered as well as its image processing application examples.

■Presenter
Yoshio Masubuchi
General Manager, Advanced SoC Development Center

Yoshio Masubuchi received B.S. and M.S. in Electronics Engineering from University of Tokyo in 1981 and 1983 respectively. Since joining Toshiba in 1983, he has been engaged in research and development of microprocessors and computer systems. From 1988 to 1990, he was a visiting fellow at University of California, Berkeley. He served as Toshiba Project Leader for the Cell project at STI Design Center in Austin, TX from 2002 to 2005. Currently, he is directing development of Advanced SoC including SpursEngine. He is a member of ACM, IEEE, Information Processing Society of Japan, and the Institute of Electronics, Information and Communication Engineers.

■MIPS Technologies, Inc.

IO Coherence in a Multi-threaded Multiprocessor: the 1004K Coherent Processing System

■Presentation Description
The presentation will discuss tradeoffs between software and hardware IO coherence with caches in a multiprocessor system, citing examples from the new multi-threaded, multiprocessor MIPS 1004K CPS.

■Presenter
Tom Berg
Staff Engineer

Tom Berg is a Staff Engineer at MIPS Technologies where he is a lead hardware developer of multi-core and IO-coherence technology. He has over 20 years of experience architecting, designing, verifying and implementing high performance coherent multi-processing computer systems and SoCs for Wang Laboratories, Sequent Computer Systems, IBM and PMC-Sierra. He holds a Bachelor's degree in Electrical and Computer Engineering from The University of Michigan and a Master’s degree in Electrical Engineering from Purdue University.
Tom Berg is a lead hardware developer of multi-core and IO-coherence technology for MIPS Technologies. He has more than 20 years of experience architecting, designing, verifying and implementing high-performance coherent multi-processing computer systems and SoCs for companies including Wang Laboratories, Sequent Computer Systems, IBM and PMC-Sierra.

■Fujitsu Laboratories LTD.

A Scalable Multicore Platforam Suitable for Embedded Systems

■Presentation Description
We introduce ARPC based multiocre platoform sutable for embedded processor system. Espacially, we explain a detail ARPC technology and some demonstration by using of Fujitsu FR-V processor.

■Presenter
Atsuhiro Suga
Director, Processing LSI Development Group, Sysytem LSI Development Laboratories

A. Suga had been developmend VLIW based FR-V processor since 1998. He also had been multicore based FR-V processor since 2003-2005. Currently we have been intrested multicore programing mode suitable for embedded processor system.

■EEMBC

Benchmarks for Analyzing Embedded Multicore Processor Capabilities

■Presentation Description
The presentation describes techniques that can be applied to measure multicore performance showing the effects of memory bandwidth, cache optimizations, programming choices, and operating system scheduling.

■Presenter
Satoshi Otsuka
Japan Regional Manager

Mr. Otsuka works as regional manager for Embedded Microprocessor Benchmark Consortium (EEMBC), US. Also he works as regional manager for Codeplay Software Ltd., UK. Besides, he is consultant for embedded system designs. Previously worked as technical directors for M-Systems Flash Disk Pioneers Ltd. (presently SanDisk) and Future Electronics in Japan.

■Tensilica Inc.

Embedded Audio Design Trade-offs via Dedicated Processors

■Presentation Description
The presentation will describe an optimized power-efficient programmable audio DSP processor architecture extending the general-purpose core Xtensa ISA with a set of audio specific instructions and architectural states.

■Presenter
Darin Petkov
Engineering Manager

Darin has worked for Tensilica since 2001, most recently designing the HiFi 2 Audio Engine and currently managing the development of audio and voice firmware. He has previous engineering experience from Synopsys and MIT and has co-authored several patents and papers. He has a B.Sc. and M.Eng. in EECS from MIT with a specialization in Computer Systems and Architectures.

■Tensilica Inc.

Xtensa Architecture in AMP and SMP Multimedia and Networking Applications

■Presentation Description
Tensilica will present architecture considerations for selection of AMP or SMP for multimedia and networking applications depending on task mix and workload stability.

■Presenter
Steve Leibson
Technology Evangelist

Steven Leibson is the Technology Evangelist for Tensilica, Inc. He formerly served as Editor in Chief of the Microprocessor Report, EDN magazine, and Embedded Developers Journal. He holds a BSEE from Case Western Reserve University and worked as a design engineer and engineering manager for leading-edge system-design companies including Hewlett-Packard and Cadnetix before becoming a journalist. Leibson is an IEEE Senior Member.

■ARC International

The VRaptor Development Platform in Multimedia and Its Development Environment

■Presentation Description
The presentation will outline ARC’s product development strategy, and provide detail about the VRaptor Development Kit (SoC architecture tool) plus implementation examples.

■Presenter
Nigel Topham
CTO

Dr. Nigel Topham is a member of the Office of the CTO and chief architect for ARC International, as well as being professor of computer systems at the University of Edinburgh. He has led a number of processor design teams, including the configurable ARC 600 processor family. Prior to joining ARC, he was chief architect for Siroyan, a startup that created a high-performance scalable VLIW DSP. He is a founding director of the Institute for Computing Systems Architecture at Edinburgh University, where he researches new design methodologies for compilers, architectures and micro-architectures. He also enjoys teaching computer architecture to the next generation of processor architects. He holds BSc and Ph.D. degrees in Computer Science, both from the University of Manchester.

■IPFlex Inc.

A Dynamically Reconfigurable Processor for Multi-Codec Applications

■Presentation Description
The presentation introduces the device architecture of the new dynamically reconfigurable processor and its core technology designed for multi-codec applications.

■Presenter
Tomoyoshi Sato
Director, Founder/CTO

In the past years he joined VMT that had Intel's compatible microprocessor buiness and there he had contributed validation methodology to guarantee full-compatibility. He joined GCT/GCL that had visual coding compression technology R&D mission for MPEG-2. He worked for the developments of MPEG-1 video decoder chip and MPEG-2 video encoder chip. After that in PDI he developed the new architecture of retargetable high performance DSP and its modeling, so called VUPU. In March of 2000, he started up IPFlex Inc. targeting dynamically reconfigurable processor business based on the DAPDNA architecture.

■Target Compiler Technologies

Implementing Application-Specific Processors and Matched Software Development Kits with the IP Designer Tool Suite

■Presentation Description
This presentation will introduce IP Designer, a retargetable tool-suite for the design, programming, and verification of Application-Specific Processors (ASIPs) in heterogeneous multi-core SoCs. IP Designer enables accurate exploration of ASIP architectures driven by a retargetable C compiler technology, power-optimized RTL implementation of ASIPs, and automatic generation of a multi-core-aware software development kit (SDK) for the implemented ASIPs.

■Presenter
Gert Goossens
CEO

Gert Goossens is the CEO and a co-founder of Target Compiler Technologies, the leading provider of retargetable tools for the design of application-specific processors (ASIPs). Before founding Target in 1996, Gert Goossens was affiliated with the IMEC research centre in Belgium, where he headed research groups on behavioural synthesis and software compilation. Gert Goossens holds several patents in the area of processor modelling and design, and has authored or co-authored around 40 papers in electronic design automation.

■TRANGO Virtual Processors

Realization of a Secure Execution Environment for DRM through the Use of a Hypervisor

■Presentation Description
Trango will present design considerations for applications where virtualization can provide a highly secure barrier protecting systems managing DRM/Crypto keys.

■Presenter
Tom Kobayashi
Acting Head of TRANGO Japan

Dr. Kobayashi joined Triangle Japan office in 2000 and provides consulting services to foreign high-tech venture-backed companies attempting to enter the Japanese market. One of the major clients is TRANGO Virtual Processors and he is Acting Head of TRANGO Japan. Prior to joining Triangle, Dr. Kobayashi served as Vice President and Deputy General Manager of Sharp Corporation's Corporate R&D group. Prior to Sharp, among other positions, at different times he was in charge of Digital Equipment Corporation's and Apple Computer's R&D in Japan.
Dr. Kobayashi has a Ph.D. from Yale University in Applied Quantum Physics. He has been active in the technical and business communities publishing over 30 technical papers all in refereed journals as well as having extensive international business development experience.

■KDDI R&D Laboratories Inc.

Technical Trend of FMBC (Fixed Mobile Broad Convergence) toward Ubiquitous Communication Era

■Presentation Description
The trend of technology about conversion of network and broadcasting and how KDDI has worked to achieve the ubiquitous network society will be the primary topics in the lecture. The contents include the architecture of FMC, FMBC, enhancement of IP core network, FTTH/CATV, broadband wireless access, and development of associated technology.

■Presenter
Hiroki Horiuchi
Dr. Eng., Executive Director
Frontier Technology Development Division, Technology Development Center

Dr. Hiroki Horiuchi graduated with a M.A. in information engineering at Nagoya University in 1985. In the same year, he entered KDD (Kokusai Denshin Denwa Co., Ltd.), which is the former company of KDDI. Since then, he has taken charge in R&D of networks and thier applied systems, such as communications protocol, network management, distributed processing, home network, and ITS (Intelligent Transport Systems). Since January 2007, he has been Executive Director of Frontier Technology Development Division at Technology Development Center.

■DxO Labs

A Programmable Scalable SIMD Image Processing Core

■Presentation Description
DxO Labs will present the DxO IPC a new configurable, programmable and scalable SIMD image processing core and imaging firmware addressing the challenges of embedded image processing.

■Presenter
Bruno Liege
COO

Bruno has 20 years of experience in the electronics and silicon industry. He holds a degree from Ecole Polytechnique in Palaiseau, France and a MS in computer architecture from Orsay University, France. He started with various technical and management positions at Thales and Tekelec Europe. After being a partner in the Apollo Invest VC fund, he became one of the founders of DxO Labs in 2003. He was Vice-President of engineering and then became COO. Bruno did the analysis that led to the IRIS approach, managed the team that implemented the first generations of tools and worked with the CTO on the DxO IPC architecture definition. Bruno holds several patents in the embedded imaging area.

■CEVA, Inc.

A DSP Architecture for HD Audio Applications

■Presentation Description
The presentation will describe applications requiring high performance and high bit accuracy and the use of a single DSP in supporting two heavy audio streams simultaneously.

■Presenter
Michael Boukaya
Director of Core Architectures

Michael Boukaya serves as Director of processor architectures at CEVA. He has nine years of experience in the semiconductor and silicon industry. Prior to this, Mr. Boukaya worked as the VLSI Project Manager of CEVA DSP cores and subsystem platforms. Previously, Mr. Boukaya worked at DSP Group, starting at 1998 as a VLSI design engineer. Mr. Boukaya holds a B.Sc. in Electrical and Computer Engineering from the Technion Institute in Israel and holds several US patents.
He serves as chief architect of the company, and in this capacity he evaluates new technologies in various domains (like Wireless emerging standards and HD video standards) and to define architecture specifications of next generation processors and multimedia platforms.
Michael was in charge for definitions and implementation of various DSP cores such as CEVA-X1620 and CEVA-X1641. In addition, Michael owns US patents in VLSI and architecture domains like a unique accelerator interface and ISA extension techniques.

■Intel Corporation

Inside the Intel ATOM Processor

■Presentation Description
The presentation will discuss some of the details of the evolution, capabilities and feature set of the new Low Power IA microarchitecture.

■Presenter
Belli Kuttanna
Chief Architect of the ATOM Processor

Belli Kuttanna is the chief architect of the ATOM processor. He is a Senior Principal Engineer and he has been with Intel for 9 years. Prior to Intel, Belli worked on several PowerPC designs while with Motorola and a SPARC CPU design with SUN Microsystems. Belli is currently working on the definition of future ATOM-based products.

■IBM Japan Ltd.

Low Power SoC Design Using PowerPC Cores

■Presentation Description
The presentation will introduce IBM's strategy for its 4xx family of embedded processor cores offering scalable performance for custom single and multi-core integrated SoC design.

■Presenter
Masahiro Murakami
Advisory R&D Engineer, AP Design Center, Microelectronics

Masahiro Murakami joined IBM Japan in 1990, after he received a Master's degree in electronics engineering. He served in LSI design and development of a system based on a LSI chip till 2001, then joined PowerPC based SoC Development Department as a SoC logic designer, verification engineer, timing engineer, and chip architect. Now he is leading PowerPC based SoC projects as a technical lead. Major SoCs he worked for are on Cell processor, consumer electronics, and Game consol aria.

■TOSHIBA Corporation

Venezia, a New Scalable Processor for Mobile Multimedia Systems

■Presentation Description
Toshiba will introduce a new scalable low power multi-core processor, Venezia, for the mobile multimedia platform using VLIW coprocessor extensions of the configurable processor MeP (Media embedded Processor).

■Presenter
Takashi Miyamori
Chief Specialist, Center for Semiconductor Research & Development

Takashi Miyamori received the B.S. and M.S. degrees in electrical engineering from Keio University, Yokohama, Japan, in 1985 and 1987, respectively. In 1987, he joined Toshiba Corporation, Kawasaki, Japan, where he was engaged in the research and development of microprocessors. From 1996 to 1998, he was a Visiting Researcher at Stanford University, Stanford, CA, where he researched reconfigurable computer architectures. He is currently a Chief Specialist and working on the development of configurable processor cores, media processors, and multimedia SoCs.

■Texas Instruments Incorporated

MSP430F5xx Generation Architecture and Overview: Breakthrough Performance for Ultra-low Power

■Presentation Description
The presentation will provide an overview of the architecture and modules of TI's 25 MIPS ultra-low power MSP430F5xx with active mode power consumption down to 160 microamps per MHz allowing it to run using solar power, vibration energy or human body temperature. The new family of chips adds to the usual integrated peripherals USB, RF, encryption and LCD interfaces.

■Presenter
Horst Diewald
Chief Architect, MSP430 Microcontrollers

In his role of the chief architect for ultra-low power MSP430 microcontrollers, Diewald is focused the future evolution of the MSP430 MCU architecture and strategy. Since joining Texas Instruments in Germany in 1972, Diewald has worked on a variety of applications and systems engineering fields.
In the early eighties, low-power product development was underway at TI, and Diewald helped develop several products with a 4-bit microcontroller core, based on TI’s TMS1000 series, for utility meter end-equipment and industrial control. In the early nineties, Diewald led the team that would define what would soon be the MSP430 MCU architecture. Over the following years, he was instrumental in defining and specifying the MCU platform's peripheral modules and products. Also during this time, the MSP430 MCU's hardware and software tool development were developed under his guidance.
Diewald was elected Member Group Technical Staff in 1991, Senior Member Technical Staff in 2000, and Distinguished Member Technical Staff in 2003.
He holds patents on the "burst-mode" concept and the integrated FLL oscillator concept. Diewald received his degree at the university of engineering in Munich, Technology of Communication.

■ARM Ltd.

Mobile Internet Devices

■Presentation Description
This presentation will discuss the mobile internet requirements and the system-level considerations needed to design a high-performance low-power SoC. Focus will be on the processor, graphics and memory subsystem and how they can best be designed with supporting IP.

■Presenter
Nigel Paver
R&D Group Consultant Engineer

Nigel Paver is a Consultant Engineering in the ARM corporate R&D group. His research interests are in system architecture, system performance and multi-media. Prior to joining ARM, he was an architect in the wireless group at Intel Corporation where he was responsible for the architecture of Wireless MMX and system architecture and analysis of the PXA 270 family of processors.
Before this Paver was one of the lead designers of the early AMULET asynchronous ARM microprocessors at the University of Manchester in England. Subsequently, he was a vice president of a start-up company that developed asynchronous design techniques and produced a low-power asynchronous DSP core. Paver has over 15 years of experience in ARM architectures.
Paver received his B.S. in electronics from the University of Manchester (U.K.) Institute of Science and Technology (UMIST). He received his M.Sc. and Ph.D. in computer science from the University of Manchester. Paver holds 14 US patents.

■ARM Ltd.

ARM Mali GPU Architecture Enables Graphics Acceleration

■Presentation Description
The presentation will cover ARM’s scalable Mali GPU architecture, future applications for graphics processing and ARM's vision for hardware graphics acceleration required for any device that has a screen.

■Presenter
Chris Porthouse
Senior Product Manager, Media Processing Division

Chris is a senior product manager in ARM’s media processing division, responsible for product management of their portfolio of graphics and Java hardware and software middleware products.
Chris has over 18 years experience in embedded systems hardware and software, in a variety of engineering, project management and product management roles. Chris has spoken at many events including Open Source In Mobile, JavaOne, Low Cost 3G Devices, Symbian Partner Event and several ARM Developer Conferences and Technical Seminars worldwide.

■Analog Devices, Inc.

Human Motion Capture Using MEMS Motion

■Presentation Description
The presentation will describe the Xsens Moven motion capture suit - a system for full-body human motion capture useful in video games, sports and motion studies.

■Presenter of In-Stat
Max Baron
Principal Analyst

■Presenter of Analog Devices K.K.
Yutaka Katano
Director, Micromachine Technology Group

Joined Analog Devices, K.K. in 1978 as field sales engineer to support direct sales business. Assigned to office manager of West-Tokyo Sales Office and Distribution Sales Management team, contributed to increase business in consumer segment. In 1994, manager in Communication Segment team, developed new business for wireless / broadband communications. In 2005 assigned to Director of Micromachine Technology Group.

■Texas Instruments Incorporated

The OMAP35x Programmable Graphics Core for OpenGL ES 2.0

■Presentation Description
TI's presentation will describe new OMAP^TM processors, based on the market's first broad offering of a programmable 3D graphics core coupled with the ARM Cortex^TM-A8, providing laptop-like performance at handheld power levels in a single chip. The advantages of the GLSL ES shading language will also be detailed.

■Presenter
Clay D. Montgomery
Graphics SW Engineer

Clay Montgomery has worked in the visual computing fields of 2D/3D graphics and digital video since 1983. His experience includes the design of 2D graphics accelerators, graphics drivers for Windows and set top box SoCs at 3Dfx Interactive, VLSI Technology, Philips Semiconductors and Texas Instruments. Most recently, he was instrumental in the first implementations of SVG and OpenGL ES applications on the OMAP2420 at the Nokia Research Center.

■Waseda University / Renesas Technology Corp.

An Eight Core - Eight-RAM SoC Delivers 8.6GMIPS and 33.6GFLOPS at 600MHz

■Presentation Description
The presentation will describe two key technologies delivering efficient parallel performance: a compiler that achieves automatic parallelization from a given source code and a standard API multicore architecture that can be programmed by the compiler.

■Presenter of Waseda University
Hironori Kasahara
Professor, Department of Computer Science and Engineering

Hironori Kasahara received B.S., M.S. and Ph.D. degrees in electrical engineering from Waseda University, in 1980, 1982, 1985 respectively. He was an Assistant Professor in 1986, an Associate Professor in 1988 and has been a Professor of Department of Computer Science since 1997 and a Director of Advanced Chip Multiprocessor Research Institute since 2004 at Waseda University. He was a Visiting Scholar at University of California at Berkeley in 1985 and a Visiting Research Scholar in 1989 to 1990 of Center for Supercomputing R. & D., Univ. of Illinois at Urbana-Champaign. He received the first Young Author Prize of IFAC World Congress in 1987 and IPSJ Sakai Memorial Special Research Award in 1997. Also he received Industry-Academia Cooperative Research Award of STARC in 2005.
He leaded Japanese Millennium Project IT21 METI/NEDO “Advanced Parallelizing Compiler” project and METI/NEDO “Multi-core for Real-time Consumer Electronics”. He served as a chair of IEEE Computer Society Japan Chapter, a Board member of IEEE Tokyo Section, a chair of the IPSJ SIG on Computer Architecture and program committees of many int'l conf. including a Vice Program Chair of ACM Int'l Conf. on Supercomputing. Also, he was a member of the Earth Simulator Advisory Committee.

■Presenter of Renesas Technology Corp.
Toshihiro Hattori
Department Manager, CPU Development Department 1

Toshihiro Hattori was received the B.S. and M.S. degrees in electrical engineering from Kyoto University, Japan, in 1983 and 1985, respectively. He received the Ph.D in informatics from Kyoto University, Japan, in 2006. He joined the Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan, in 1985. He engaged in logic/layout tool development. From 1992 to 1993 he was a Visiting Researcher at the University of California Berkeley. He joined the Semiconductor Development Center in the Semiconductor Integrated Circuits Division in Hitachi Ltd. in 1995. He moved to Renesas Technology Corp. in 2003. He was belonging to SuperH (Japan), Ltd. from 2001 to 2004 to conduct SH processor licensing and development. He is currently working with Renesas Technology conducting CPU core design, SH-mobile design and Multi-media Soc design. He is heading SH-multi-core PJ including hardware and software viewpoints.