Microprocessor Forum Japan 2008

Wednesday July 16, 2008
Thursday July 17, 2008

■Wednesday July 16, 2008

9:30 AM	10 min.	E	Welcome and Intro Max Baron Principal Analyst In-Stat
Keynote
9:40 AM	50 min.	E	Technology Changes and Challenges Ton Steenman Vice President, Digital Enterprise Group General Manager, Infrastructure Processor Division Intel Corporation
Session One High Performance General-Purpose Embedded Multi-core Systems
10:30 AM	35 min.	E	ARM's MPCore Architecture Performance Enhancements John Goodacre Senior Program Manager ARM Ltd.
11:05 AM	15 min.		Break
11:20 AM	35 min.	J	New Stream Processor "SpursEngine" Yoshio Masubuchi General Manager, Advanced SoC Development Center TOSHIBA Corporation Semiconductor Company
11:55 AM	35 min.	E	IO Coherence in a Multi-threaded Multiprocessor: the 1004K Coherent Processing System Tom Berg Staff Engineer MIPS Technologies, Inc.
12:30 PM	65 min.		Lunch
1:35 PM	35 min.	J	A Scalable Multicore Platforam Suitable for Embedded Systems Atsuhiro Suga Director, Processing LSI Development Group Sysytem LSI Development Laboratories Fujitsu Laboratories LTD.
2:10 PM	35 min.	J	Benchmarks for Analyzing Embedded Multicore Processor Capabilities Satoshi Otsuka Japan Regional Manager EEMBC
Session Two Configurable Extensible Processors for Multimedia Applications
2:45 PM	35 min.	E	Embedded Audio Design Trade-offs via Dedicated Processors Darin Petkov Engineering Manager Tensilica Inc.
3:20 PM	20 min.		Break
3:40 PM	35 min.	E	Xtensa Architecture in AMP and SMP Multimedia and Networking Applications Steve Leibson Technology Evangelist Tensilica Inc.
4:15 PM	35 min.	E	The VRaptor Development Platform in Multimedia and Its Development Environment Nigel Topham CTO ARC International
4:50 PM	35 min.	J	A Dynamically Reconfigurable Processor for Multi-Codec Applications Tomoyoshi Sato Director, Founder/CTO IPFlex Inc.
5:25 PM	35 min.	E	Implementing Application-Specific Processors and Matched Software Development Kits with the IP Designer Tool Suite Gert Goossens CEO Target Compiler Technologies
Session Three DRM and Security in Silicon and in Software
6:00 PM	35 min.	J	Realization of a Secure Execution Environment for DRM through the Use of a Hypervisor Tom Kobayashi Acting Head of TRANGO Japan TRANGO Virtual Processors

6:35 PM			Cocktail Party

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■Thursday July 17, 2008

9:30 AM	10 min.	E	Welcome and Intro Max Baron Principal Analyst In-Stat
Keynote
9:40 AM	50 min.	J	Technical Trend of FMBC (Fixed Mobile Broad Convergence) toward Ubiquitous Communication Era Hiroki Horiuchi Dr. Eng., Executive Director Frontier Technology Development Division Technology Development Center KDDI R&D Laboratories Inc.
Session Four New Chips and Cores for Audio/Video and Photo Processing
10:30 AM	35 min.	E	A Programmable Scalable SIMD Image Processing Core Bruno Liege COO DxO Labs
11:05 AM	15 min.		Break
11:20 AM	35 min.	E	A DSP Architecture for HD Audio Applications Michael Boukaya Director of Core Architectures CEVA, Inc.
11:55 PM	65 min.		Lunch
Session Five Chips and Cores for Mobile Systems
1:00 PM	35 min.	E	Inside the Intel ATOM Processor Belli Kuttanna Chief Architect of the ATOM Processor Intel Corporation
1:35 PM	35 min.	J	Low Power SoC Design Using PowerPC Cores Masahiro Murakami Advisory R&D Engineer, AP Design Center, Microelectronics IBM Japan Ltd.
2:10 PM	35 min.	J	Venezia, a New Scalable Processor for Mobile Multimedia Systems Takashi Miyamori Chief Specialist Center for Semiconductor Research & Development TOSHIBA Corporation
2:45 PM	35 min.	E	MSP430F5xx Generation Architecture and Overview: Breakthrough Performance for Ultra-low Power Horst Diewald Chief Architect, MSP430 Microcontrollers Texas Instruments Incorporated
3:20 PM	20 min.		Break
3:40 PM	35 min.	E	Mobile Internet Devices Nigel Paver R&D Group Consultant Engineer ARM Ltd.
Session Six Graphics' Chips, Cores and Video Game Creation Using MEMS and Processors
4:15 PM	35 min.	E	ARM Mali GPU Architecture Enables Graphics Acceleration Chris Porthouse Senior Product Manager, Media Processing Division ARM Ltd.
4:50 PM	35 min.	E J	Human Motion Capture Using MEMS Motion Sensors Max Baron Principal Analyst In-Stat Yutaka Katano Director, Micromachine Technology Group Analog Devices K.K.
5:25 PM	35 min.	E	The OMAP35x Programmable Graphics Core for OpenGL ES 2.0 Clay D. Montgomery Graphics SW Engineer Texas Instruments Incorporated
6:00 PM	35 min.	J	An Eight Core - Eight-RAM SoC Delivers 8.6GMIPS and 33.6GFLOPS at 600MHz Hironori Kasahara Professor, Department of Computer Science and Engineering Waseda University Toshihiro Hattori Department Manager, CPU Development Department 1 Renesas Technology Corp.

6:35 PM			Adjourn

*Note 1: Agenda is subject to change.
*Note 2: E = English, J = Japanese.
*Note 3: Simultaneous interpretation between English and Japanese will be provided for all presentations.

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