■Toshio Mii, IBM

Director, Technology Alliances, Global Engineering Solutions “From Process Development to Consumer Products: How Collaboration Makes a Difference” ■Abstract of Presentation Research has shown that innovation that matters in the marketplace is not confined to a single company or its R&D function. Employees, business partners, and clients can provide a wealth of ideas that can lead to products and solutions that the market requires. This isn't optional, the market demands collaborative innovation to bring the best of the ecosystem together to provide innovative solutions. This presentation will discuss the Common Platform Technology Alliance and how collaborative innovation addresses market requirements. ■Speaker’s Bio Toshio Mii is Director, Technology Alliance of Common Platform organized by three companies; IBM, Chartered Semiconductor Manufacturing and Samsung Electronics Co., Ltd. After he joined IBM US, he worked on development of DRAM process and technology transfer. In 2002, he was in charge of Engineering Technology Service in IBM Japan. Since he returned to IBM US in 2005, he has been involved in project planning of system development services applied with Cell Processor. He holds a Ph.D. in Electrical Engineering from Duke University.

■Vivek De, Intel

Intel Fellow & Director of Circuit Technology Research “Beyond Multi-Core: The Dawning of the Era of Tera” ■Abstract of Presentation The Intel Tera-scale Computing Research Program is a worldwide research effort to create platforms for the next decade with 10s to 100s of cores and capabilities only dreamt of today. Learn about Intel’s research vision and how an 80-core research processor commences the “Era of Tera” with teraflops performance, a terabit/second on-chip interconnect fabric, and remarkable energy efficiency. ■Speaker’s Bio Vivek De is an Intel Fellow in the Circuits Research Lab in Hillsboro, Oregon. He joined Intel in 1996 as a staff engineer working on low power and high performance circuits research. He received his Ph.D. in Electrical Engineering from Rensselaer Polytechnic Institute, Troy, New York.

■Atsuhiro Suga, FUJITSU LABORATORIES LTD.

Director, Processor Solution Development Lab., System LSI Development Laboratories “Fujitsu Embedded Heterogeneous Multicore Solution” ■Abstract of Presentation In multi-core processing that is been paid attention, there are two types architectures: SMP type and AMP type. The SMP type architecture place the same cores on a shared memory, and the AMP type different cores on different memories. When a designer wants to port a multi-tasked program from a single core to multi-cores, the SMP type architecture is suitable. When he/she wants to port a single program from a single core to multi-cores, he/she has to change a lot of description in a program. We propose a multi-core technology which can support to change a number of cores scalablly while minimizing software change operation in case of porting to multi-cores using existing OS and a single program. We will talk about a programming model, its implementation method, operation examples and performance evaluation environment, in case study of multiple ARM core processor platform. ■Speaker’s Bio He is a Director in the System LSI Development Laboratories at Fujitsu Laboratories Limited in Kawasaki, Japan. His research interests include microprocessors and architecture for digital consumer products.

■Tomoyoshi Sato, IPFlex Inc.

Vice President and Chief Technology Officer “A Multi-Core Dynamically Reconfigurable Engine with Flexible (955) Parallel Processing Elements DAPDNA-IMX” ■Abstract of Presentation This presentation is the first disclosure of IPFlex’s dynamically reconfigurable processor targeted to provide high-performance programmable processing that is difficult to obtain via conventional ASICs. The presentation will provide detail on the engine’s processing capability plus application examples. ■Speaker’s Bio Mr. Sato has been involved in development of Intel386 compatible processors, MPEG1/2 encoder chip, and then he founded IPFlex, a startup focusing on dynamically reconfigurable processor business in March 2000.

■Gary Brown, Stream Processors Inc.

Japan Country Manager “Making Parallel Processing Simple -- Storm-1 SP16HP: A 112 GMACS, C Programmable, Media and Signal Processor” ■Abstract of Presentation SPI will announce and describe the new SP16HP-G220, the flagship device of the Storm-1 family, featuring leading signal processing capabilities of up to 112 GMACS for 16-bit operands or 440 GOPS for 8-bit data. ■Speaker’s Bio Gary Brown is currently dedicated to SPI's Japan business, with over sixteen years experience in DSP and microprocessor technology. Early in his career while at Matsushita Electric's semiconductor research center, he developed and patented a random test method for microprocessors. He returned to the US to serve in applications engineering leadership roles at Dolby Laboratories, Tensilica, and later at Arithmatica, supporting customer and partner relationships in North America and Japan, before joining SPI two years ago. Gary holds a BS in Engineering Mathematics from University of California at Berkeley and an MSEE from Stanford University.

■Hiroyuki Kataoka, Boston Circuits, Inc.

President & CEO “Seamless Integration of Multi-Cores” ■Abstract of Presentation Seamless integration of multiple processor cores in both hardware and software is the key to achieving success in both developing and using multicore processors. This technical presentation describes how Boston Circuits has implemented a "Grid on Chip" architecture to integrate 16 cores, and how its "Time Machine" module enables seamless integration of software over these multiple cores by dynamically scheduling threads and allocating resources in hardware. ■Speaker’s Bio Hiro Kataoka is President and CEO, Boston Circuits, Inc. He has established himself in the technology business on both sides of the Pacific in his 20 year career. In 1991, Hiro founded Dimatech Corporation, to provide semiconductor, software, and embedded system solutions for the digital imaging market. The company was acquired by NetSilicon, Inc. in 2001 where Hiro served as Vice President of Worldwide Sales.

■John Goodacre, ARM

Program Manager, Multiprocessing “Multi-Processor Extensions to the ARMv7 Architecture” ■Abstract of Presentation This presentation is the first disclosure of new extension to the ARMv7 architecture that form the basis for further ARM multi-processors. It also explores the fundamental requirements of multi-processor systems and reviews existing hardware and software implementations. “A New ARM Processor for Synthesis on FPGA” ■Abstract of Presentation This paper provides an overview of the technology applied to enable the creation of an ARM processor designed for synthesis on FPGA. ■Speaker’s Bio John Goodacre is responsible for the development of ARM's multiprocessing technology. Prior to joining ARM in 2002, he managed the Microsoft Wireless Telephony group responsible for strategy of mobile devices. Graduating from the University of York with a BSc in Computer Science, John has over 20 years experience in the engineering industry.

■Maurice Steinman, AMD

AMD Fellow “Next-Generation Mobile Computing: Balancing Performance and Power Efficiency” ■Abstract of Presentation AMD will introduce a new method of power savings in which the processor is freed from reliance on operating system software to coordinate the use of energy. ■Speaker’s Bio Maurice Steinman is an AMD Fellow with chief responsibility for the design of AMD’s next-generation mobile microprocessor portfolio. In this role Maurice leads development activities for AMD’s new mobile optimized on-die Northbridge and microprocessor architecture from planning to implementation. Prior to joining AMD, he was a Senior Engineer at Intel Corporation focused on next-generation microprocessor architecture development. Before joining Intel, he held senior engineering positions at HP/Compaq as well as Digital Equipment Corporation. Maurice holds 14 patents with an additional six pending in the areas of microprocessor design and architecture and holds a B.S in Computer and Systems Engineering from Rensselaer Polytechnic Institute.

■Robert J. Mears, MEARS Technologies

President & CTO “New Semiconductor Technology Enhances Drive Current, Lowers Leakage” ■Abstract of Presentation MEARS Technology will present a method of device scaling below 45nm, that incorporates a new technique to enhance drive current and mitigate microprocessor gate leakage through insertion of a high-mobility epitaxial silicon-channel replacement layer, which involves no new elements in the fabrication process. ■Speaker’s Bio Dr. Robert J. Mears, our founder, has been leading the creation of the MST platform since 2001. He has a track record of developing industry shaping technologies and is recognized as one of the world’s leading experts in photonics - the synthesis of electronics and optical communications. In the late 1980’s, Dr. Mears addressed the challenge of expanding the bandwidth of fiber optic cable by inventing the Erbium Doped Fiber Amplifier (“EDFA”). He has authored or co-authored approximately 150 publications and numerous patents and is an Emeritus Fellow of Pembroke College, Cambridge, England.

■Vidya Rajagopalan, MIPS Technologies, Inc.

Director of Engineering “New Area and Power-Efficient MIPS Processors Achieve High Performance” ■Abstract of Presentation MIPS Technologies will launch its new generation of single-threaded, high-performance processor cores designed to optimize die area and power. ■Speaker’s Bio Vidya Rajagopalan is an engineering director at MIPS Technologies, where she has been responsible for the definition and management of MIPS’ next-generation core family. Previously, she was responsible for the MIPS64R 20Kc product line at MIPS. Rajagopalan was previously employed at QED and Digital Equipment Corporation. At Digital Equipment, she was involved in the design and definition of several implementations of the Alpha architecture including the 21064 and 21164 products. Rajagopalan has a masters degree in electrical engineering from the University of Maryland, College Park.

■Hideaki Ishihara, DENSO CORPORATION

Senior Manager of IP R&D Center, IC Engineering Department 1 “Future Prospects of Automotive Electronics and Expectations for Microprocessor Technologies” ■Abstract of Presentation Automotive electronics have been rapidly advancing in their successful pursuit of environmental friendliness, safety, convenience, and comfort. Such advancements were achieved through the use of around one hundred processors per luxury car. Automotive processors are required to have a high level of performance and reliability, while remaining cost efficient. These processors must also have high affinity with automotive control software, and be capable of real time processing. The processors used in the GPS navigation and image recognition are developed to have extremely high capabilities in parallel processing. In this presentation, the speaker will talk about the major roles and expectations of microprocessor technologies in automotive embedded systems. He will also give a comparison between the proprietary 32-bit RISC processor and other major processors. Finally, he will talk about: functional safety; automotive LAN & multi-core computing; chip-sets embedded with sensors and actuators; and system LSI design methodologies. ■Speaker’s Bio Mr. Ishihara has been a senior manager at the IP R&D Center, IC Engineering Department at DENSO, since 2001. He has been responsible for developing System LSI designs in automotive electronics. He has developed proprietary 8-bit and 32-bit microprocessor cores applied to automotive systems such as: power train, body control, safety control, and ITS systems embedded in a wide variety of vehicles. These are widely used by many automotive manufacturers including Toyota. Furthermore, he has developed many kinds of technologies including EMC technology, automotive network LSI, analog LSI, and system LSI design methodologies. He received his Master’s degree from Nagoya University, and joined DENSO in the same year.

■Yoshiyuki Matsumoto, Renesas Technology Corp.

Group Manager, Car Information System Design Dept. System Solution Business Unit4, System Solution Business Group “SH-Navi2V: A Car Navigation Processor Employing a 38.4GOPS Image Recognition Engine” ■Abstract of Presentation Renesas has developed a car navigation ASSP with 600MHz superscalar CPU Core SH4A on it. Furthermore, this ASSP has a parallel image recognition engine with the peak performance of 38.4GOPS. The image processing kernel codes are executed here while the decision requiring intelligence is performed by the CPU. To save the cost, unified memory architecture has been applied with a split-transaction, multi-channel on-chip interconnect fabric. The ASSP comes also with two more accelerator engines, the x8 realtime AAC encoder engine and a 2D graphics engine for the 60fps class of fast WVGA size map update. ■Speaker’s Bio 1985     Joined Hitachi, Ltd. 1986     Served in LSI design on digital video and applied development 1995     Served in LSI technology for CIS, LSI planning and design development 2003     Transferred to Renesas Technology Corp. with its foundation Design development manager on LSI SH-Navi Series for CIS

■Jeff Maguire, Freescale Semiconductor

Chief Architect “Automotive-Qualified Multi-core Microprocessors for Telematics and Industrial Control Systems” ■Abstract of Presentation Freescale will unveil two new SoC microprocessors designed for the telematics and automotive navigation markets, as well as networked industrial control applications. ■Speaker’s Bio Jeff Maguire serves as Chief Architect in TSPG’s Infotainment, Multimedia & Telematics Operation at Freescale Semiconductor. His responsibilities include SoC architecture, process technology strategy and IP research/acquisitions targeted at high-performance automotive applications. He holds a BSEE from UC Berkeley, MSEE from NTU and seven patents. His eighteen-year career includes microprocessors / mixed-signal / SoC development, low-power research, coding standards and tool flows.

■Nico Kelling, Infineon Technologies Japan

Senior Manager, Automotive Microcontroller “Architectural Solutions for Safety and High-end Development Support in Today’s and Upcoming Multicore Designs” ■Abstract of Presentation This presentation will address two key challenges and solutions for present and future microcontroller based designs. It will address the requirements and solution for accurate debugging, emulation and calibration in modern high performance and often multicore, high-frequency architectures under special attention to the constraints in automotive real-time embedded development environment. The requests for cost effectiveness and interface harmonization will be discussed and a new interface standard will be introduced that allows to broaden this approach even beyond single chip implementations, including transputer implementations. Further, a unique new solution single chip solution will be presented to facilitate the certifiable implementation of a true safety systems satisfying new 61508 functional safety standard (SIL3). Existing production silicon will be used to demonstrate the claims made. ■Speaker’s Bio Nico Kelling graduated in Technical Computer Science in Germany. He is founder and president of “NKE-Software” engineering company since 1993 and joined Infineon (Siemens-HL at the time) in 1997. After work in microcontroller product definition, he supported lead customer as technical program manager in Indiana/USA. In 2000, back in Munich, he became project leader for the European research project “BRAKE”, developing a distributed x-by-wire braking prototype based on fault-tolerant communication technology. In 2002, he became responsible for powertrain system marketing and later was promoted to head of system marketing, covering powertrain, chassis and safety applications. Since 2006, Nico Kelling is heading the microcontroller activities in Japan. Nico Kelling has authored numerous publications and is a contributing member to the society of automotive engineers (SAE) since 1999.

■Atsushi Yamada, IBM Japan

Senior Researcher, Model-Driven Systems Engineering Tokyo Research Laboratory “AUTOSAR-A Major Shift in the Automotive Industry” ■Abstract of Presentation After a short introduction to the overall objectives and structure of AUTOSAR (Automotive Open System Architecture), the paper will especially present the basic software layer concept of AUTOSAR. Special attention will be paid on the microcontroller abstraction layer and its components and on the ECU (electronic control unit) abstraction layer, both interfacing hardware components. Further on the results of AUTOSAR phase 1 in total will be summarized and an outlook on the activities of the AUTOSAR phase 2 will be provided. The participation and contribution of IBM as AUTOSAR Premium Member will be presented. The IBM offerings for AUTOSAR will be presented. Some vision statements about the changes in the automotive in-vehicle electronic landscape will finalize the presentation. ■Speaker’s Bio Atsushi Yamada joined IBM Tokyo Research Laboratory in 1995, after he received a Master’s degree and Ph. D. in mechanical engineering. Since then, he has been in charge of R&D of design development in the automotive applications. Currently he is involved in expanding the model-driven systems engineering based on the SysML language specification into the manufacturing industry.

■Koji Chiba, NTT DoCoMo

Deputy Managing Director of Communication Device Development Department "3G Evolutional Innovation toward 4G services - Super3G & 4G" ■Abstract of Presentation NTT DoCoMo's keynote will inform attendees on the status of Super 3G and 4G cellular phone technologies, and the tests and experiments carried out to date. The service providers' requirements of functions that must be provided by cell phone processors during the next few years will also be addressed. The migration toward 4G providing up to 1.0 Gb/s data communications will affect all computers, not just cell phones. ■Speaker’s Bio Koji Chiba is Deputy Managing Director of Communication Device Development Department, NTT DoCoMo, R&D center. He joined Electrical Communication Lab., NTT Public Corp in 1980. Then, he worked on research and development of 2nd generation, pocket-bell and satellite communication terminal equipment. He is currently involved design and development of 3rd and 3.9rd generation hand-set terminals.

■Junko Sunaga, Qualcomm CDMA Technologies

Director, Marketing “Qualcomm's Chipset Planning Concept for Wireless Mobile Terminal and Snapdragon Product Line” ■Abstract of Presentation CDMA network technology has made progress, such as realizing efficient and low-cost transmission and secured transmission/reception for thin data through QoS, as market needs grow. To service providers, offering various services using such features of CDMA network and seamless service connection with other wireless networks is becoming increasingly important as service differentiation against competitions. It is essential requirement for a service provider and a handset manufacture to realize time-to-market launch of small form factor and rich featured handsets of low power consumption, yet for a low cost. I would like to explain on how Qualcomm plans to offer its solution to such market requirements also the 1GHz Scorpion core embedded Snapdragon chip. ■Speaker’s Bio She jointed NEC Corporation on 1983 as an application engineer for DSP based LSIs, also was involved into software development of PDC/GSM baseband LSI. From 1993-1996, She was assigned to System Application Engineering Department at Mountain View, California. In her position as Application Manager, She was responsible for chipset specification development and customer supports for IS-54/IS136, which use DSP and AD MIX LSIs. 1996, She was assigned to Cellular Systems Engineering Department, Semiconductors Solution Engineering Division. She was responsible for product planning of GSM, US cellular/PCS. She jointed Qualcomm Japan on 1997 as a manager for marketing, and she has been involved into product planning of CDMA baseband chip, multimedia embedded into the CDMA chip also marketing and carrier relations. Now she is responsible for CDMA chipset, multimedia and software product as a director of marketing.

■Taku Ohsawa, NEC Electronics Corporation

SoC System Division, 2nd SoC Operation Unit “Parallelization Technologies for a Mobile Application Chip” ■Abstract of Presentation Application processors designed for mobile phone applications are required to higher performance, lower power dissipation to meet a wide variety of applications. NEC Electronics continues to develop parallel processing technologies for higher performance and lower power dissipation by ushering in multi-processor technologies. This presentation will introduce a next generation mobile application chip architecture that features communication and application functions in a single chip. Parallel processor technologies and low power dissipation technologies adopted in the architecture will also be presented. ■Speaker’s Bio Taku Ohsawa joined NEC in 1998. He worked on research and development of automatically parallel-processed multiprocessor at System Devices Research Laboratories. In 2005, he joined NEC Electronics and was involved in development of Medity chipset for mobile applications.

Note: Agenda subject to change.